1. Field of the Invention
The invention relates to integrated circuits for use in optical transceivers, and in particular to Ethernet (IEEE 802.3ae standard) compliant transceivers that provide a 10 Gigabit per second communications link between computers or communications units over optical fibers, such as used in high throughput fiber optic communications links in local and wide area networks and storage networks.
2. Description of the Related Art
A variety of optical transceivers are known in the art which include an optical transmit portion that converts an electrical signal into a modulated light beam that is coupled to a first optical fiber, and a receive portion that receives a second optical signal from a second optical fiber and converts it into an electrical signal.
Optical transceivers are packaged in a number of standard form factors which are “hot pluggable” into the chassis of the communications data system unit. Standard form factors provide standardized dimensions and electrical input/output interfaces that allow devices from different manufacturers to be used interchangeably. Some of the most popular form factors include XENPAK (see www.xenpak.org), X2 (see www.X2 msa.org), SFF (“small form factor”), SFP (“small form factor pluggable”), and XFP (“10 Gigabit Small Form Factor Pluggable”, see www.XFPMSA.org).
Although these conventional pluggable designs have been used successfully in the past for low data rate protocol, challenge miniaturization for which is an ever-constant objective in the industry. It is desirable to miniaturize the size of transceivers in order permit greater port density associated with the electrical network connection, such as, for example, the input/output ports of switch boxes, cabling patch panels, wiring closets, and computer I/O interfaces.
The XFP module is a hot-pluggable, serial-to-serial optical transceiver that supports SONET OC-192, 10 Gigabit Ethernet, 10-Gbit/s Fiber Channel, and G.709 links. The module is 78 mm in length, 18.4 mm in width, and 8.5 mm in height. This small size limits the amount of electrical circuitry that can be implemented in the package, and consequentially in the prior art the majority of electronic signal processing is located in devices on the host board (inside the computer or network unit) rather than within the module in current commercial XFP devices. The XFP form factor features a serial 10 Gbit/s electrical interface called XFI that assumes that the majority of electronic signal processing functions are located within the circuits or ASICs on the system printed circuit board rather than within the optical transceiver module. Since the electronic processing defines the communication protocol, the XFP module is protocol independent.
The XFI interface is a differentially signaled, serial interconnect with nominal baud rate between 9.95 and 10.75 Gbit/s. Transmit and receive signals are AC coupled, 100-ohm differential pairs. The electrical interconnect may include combinations of microstrip and/or stripline traces on the printed circuit board up to 12 in. (300 mm) in length, layer-to-layer via structures, a 30-pin connector, and a BGA ASIC package.
One of the most important optical communications protocols is the 10 Gigabit per second Ethernet standard (GbE) is particularly suited for this technology.
10 Gigabit Ethernet standard specifications are set forth in the IEEE 802.3ae supplement to the IEEE 802.3 Ethernet standard. The supplement extends the 802.3 protocol and MAC specification to an operating speed of 10 Gb/s. Several Physical Coding Sublayers known as 10 GBASE-X, 10 GBASE-R and 10-GBASE-W are specified, as well as a 10 Gigabit Media Independent Interface (XGMII), a 10 Gigabit Attachment Unit Interface (XAUI) a 10 Gigabit Sixteen-Bit Interface (XSBI) and management.
The 10 GBASE-LX4 media type uses wave division multiplexing technology to send signals over four wavelengths of light carried over a single pair of fiber optic cables. The use of course wavelength division multiplexing (CWDM) allows four optically multiplexed channels each transmitting a 3.125 Gb/sec signal over a single fiber pair (i.e. utilizing one fiber for each direction), as set forth in IEEE 802.3ae Clause 53, setting forth the 10 GBASE-LX4 Physical Media Dependent (PMD) sublayer. An optical transceiver designed for operating in conformance with such protocol is described in U.S. patent Ser. No. 10/866,265, herein incorporated by reference. The 10 GBASE-LX4 system is designed to operate at 1310 nm over multi-mode or single-mode dark fiber. The design goal for this media system is from two meters up to 300 meters over multimode fiber or from two meters up to 10 kilometers over single-mode fiber, with longer distances possible depending on cable type and signal quality requirements.
WDM high date rate applications have found widespread application in short reach Ethernet networks. Ethernet (the IEEE 802.3 standard) is the most popular data link network protocol. The Gigabit Ethernet Standard (IEEE 802.3) was released in 1998 and included both optical fiber and twisted pair cable implementations. The 10 GB/sec Ethernet standard (IEEE 802.3 ae) was released in 2002 with both optical fiber and twisted pair cabling. The difficulties associated with multi-gigabit signaling over existing wiring has limited the applications for such cabling, although efforts are currently underway for new copper cabling standards.
Among the many features defined in the 10 Gigabit Ethernet draft standard is the XAUI (pronounced “Zowie”) interface. The “AUI” portion of the acronym is borrowed from the Ethernet Attachment Unit Interface. The “X” in the acronym represents the Roman numeral for ten and implies the interface is ten gigabits per second. The XAUI interface is a low pin count, self-clocked serial bus designed as an Interface extender for the 74 signal wide interface (32-bit data paths for each of transmit and received) XGMII. The XAUI may be used in place of, or to extend, the XGMII in chip-to-chip applications typical of most Ethernet MAC to PHY interconnects
In the transmit direction, the MAC parallel electrical interface (XAUI) is monitored and retimed by the physical layer device (PHY). The XAUI bus is a four lane, 8b/10b encoded, 3.125 Gb/s CML electrical signal. Much like scrambling in traditional SONET systems, 8b/10b encoding ensures DC-balance (the average number of logic ones is equal to the average number of logic zeros) and a minimum transition density simplifying the optical architecture. The retimed XAUI bus modulates an optical transmitter array, generating four optical Non-Return-to-Zero (NRZ) waveforms. Each optical transmitter operates at a different wavelength, near 1310 nm with 24.5 nm center spacing and 13 nm tolerance. The optical signals are wavelength division multiplexed for transmission over a single fiber.
In the received direction, the CWDM signal is optically demultiplexed into its four constituent wavelengths. A quad receiver array converts the demultiplexed optical signals into four 3.125 Gb/s electrical signals. The PHY device performs clock recovery on each data lane, retimes the signal, and monitors the network interface performance. The retimed XAUI interface is then transmitted to the MAC device.
The fact that 10 GBASE-LX4 is simply an optical extension of the XAUI interface often calls into question whether or not the PHY device is always required. In fact, IEEE 802.3ae does not explicitly define a requirement for the PHY device and remains intentionally vague on the implementation details. However, the PHY device performs two very important tasks, which cannot be easily addressed in its absence.
First, the XAUI interface was originally defined to extend the system reach between layer 2 and layer 1 devices while simultaneously reducing the pin count requirements of small form factor pluggable modules. This interface is loosely defined to support 50 cm (twenty inches) of FR-4 material. In a typical 10 GBASE-LX4 module-based implementation, the XAUI interface would be subject to transmission distances on the order of 10 cm (4″) on each of four independent substrates, plus two connector interfaces. With additional penalties due to the electrical-to-optical and optical-to-electrical conversion combined with impairments introduced by the transmission media, XAUI amplitude and phase noise limits will likely be exceeded. Highly integrated PHYs, such as the Quake Technologies (QT2044, provide full 3R (recover, retime, reshape) regeneration with compliance to the IEEE 802.3ae 10 GBASE-LX4 and XAUI specifications.
Secondly, the 10 GBASE-LX4 standard also requires conformance to the XGXS and PCS/PMA physical layer clauses, which contain an extensive set of registers for provisioning and performance monitoring. The majority of these registers is associated with XAUI performance and is best handled within a high-speed PHY device. In addition, PHY devices specifically designed for 10 GBASE-LX4 applications, such as the QT2044, integrate management for the pluggable module non-volatile memory space and Diagnostic Optical Monitoring (DOM) devices defined within the XENPAK, XPAK, and X2 Multi-Source Agreements.
The electrical input to the optical transceiver is a serial 10 Gbit/sec XFI interface. In order to produce a 10 GBASE-LX4 optical signal, the electrical input must be converted into a four lane XAUI signal, with each lane applied to and modulating a different laser.
Although single chip integrated circuits such as the Puma AEL1002 are commercially available, such chips are designed for implementation on the host side, and convert four lanes of 3.125 Gbps/XAUI data signals from the host into a 10 Gbps XFI data signal which is applied to the XFP module, as shown in FIG. 1. Since the optical signal being transmitted by such existing modules is a serial 10 Gbps signal, there has been no need for an XFI to XAUI data signal conversion.
Prior to the present invention, there has not been a suitable integrated circuit for use in a transceiver for high speed (10 Gigabits/sec. or more) optical transmission in a very small (XFP type) form factor.